1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to integrated circuits implementing high density transistors having increased channel widths.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, are widely used for storing data in systems such as computer systems. A DRAM memory cell typically includes an access device such as a field effect transistor (FET) coupled to a storage device such as a capacitor. The access device allows the transfer of charges to and from the storage capacitor thereby facilitating read and write operations in the memory device. The memory cells are typically arranged in a number of rows and columns to provide a memory array.
With the constantly increasing demand for higher data storage capacity, memory arrays are becoming more dense. Memory density is typically limited by current processing technologies implemented to fabricate the memory arrays. Typical memory cell array topologies provide for feature sizes (F) which are limited by the width of the electrically conductive word lines and bit lines in the array, and the width of the isolation regions between the word lines and bit lines. Conventional array topologies provide for cell sizes on the order of 8F2. While this may be acceptable in most applications, a reduction in feature size, thereby enabling an increase in memory density, may be desirable.
Still further, increasing the density of the memory arrays without sacrificing performance capabilities is generally desirable. Among the concerns in fabricating memory devices is to provide memory cells with minimal leakage to prevent the loss of storage cell data. Further, alpha-particle induced soft errors which alter the data stored in the memory cells should also be considered, and simplification in fabrication techniques may also be desirable.
One technique for fabricating DRAM cells implements planar access transistors. As will be appreciated, sub-threshold characteristics and threshold characteristics greatly affect DRAM devices. Disadvantageously, improving sub-threshold characteristics may adversely affect threshold characteristics. Sub-threshold (off-state) characteristics of planar DRAM devices are closely associated with the device's ability to meet refresh requirements. Further, for low power applications, scaling down the threshold voltage of the DRAM device is important in accommodating low Vcc requirements. Over the past several generations (0.35 to 0.10 um technologies), access device threshold and sub-threshold voltages have not scaled down fast enough to meet these conflicting design specs.
Further, the performance of complimentary metal oxide semiconductor (CMOS) devices in the periphery portions of a DRAM may be constrained due to several unique processing steps in fabrication of the DRAM device. In particular, highly resistive polysilicon plug processes for providing access to the sources/drains of buried transistors, non-salicided active areas, back end heat steps, deactivating anneals, etc., place limits on periphery device performance. It is desirable to have a process flow that does not compromise periphery logic while achieving acceptable characteristics for the access devices in the memory array.
Off-state characteristics in a MOS transistor are largely determined by the extent to which the gate controls the charge density in the channel region. Reducing gate oxide thickness increases the gate capacitance and therefore increases gate control. Double-gate or dual-gate transistors may be implemented to further increase gate control and reduce short channel effects but double gate transistors are often complex to manufacture and may not be practical in many applications. One type of double-gate structure implements FETs fabricated on silicon-on-insulator (SOI) substrates. Unfortunately these devices suffer from severe reduction in drive currents unless several “fins” are constructed along the width direction of the access device. These devices are generally referred to as “FinFETs,” as will be appreciated by those skilled in the art. In a large width logic device, constructing several fins might be possible. However, in dense drives, such as DRAM arrays, the additional real estate that would be occupied by the additional fins makes the device impractical in such high density applications.
Further, implementing SOI substrates, rather than bulk silicon to fabricate DRAM devices introduces a number of design and operation issues. One consideration in implementing SOI devices is the floating body effect (FBE) due to lack of body contact. Controlling the FBE is one consideration in the integration of SOI devices in a DRAM process. As will be appreciated, fully depleted SOI devices generally exhibit less FBE. However, very thin silicon films are generally necessary for full depletion and this potentially introduces large variation in device characteristics for small variation in silicon film thickness. Even for relatively long devices (e.g., 0.25 um), large increases in sensitivity of threshold voltage to silicon film thickness generally occur.
Still further, as gate oxide thickness is scaled down to increase gate capacitance (and therefore, increase gate control of the channel region), several additional problems may arise. Poor gate oxide integrity, poor gate oxide life, direct tunneling due to high electric fields (gate current), soft breakdown, etc. are all considerations in DRAM device design and operation. In addition, for dual-gate polysilicon processes implementing both n+ and p+ gate polysilicon, boron penetration from the p+ polysilicon gate through the gate oxide into the channel may be problematic. To minimize boron diffusion, nitrided gate oxides may be implemented. Disadvantageously, for very thin gate oxides (e.g., less than 35 angstroms), the nitridation process (e.g., RPN, DPN) introduces a large number of trap states in the oxide and therefore further degrades oxide quality.
High dielectric constant materials like zirconium oxide, hafnium oxide and aluminum oxide have been proposed as replacement for silicon-dioxide (SiO2) which is generally implemented to form the gate oxide. However, these materials have poor quality interface compared to SiO2 and therefore severely degrade mobility in the channel. For this reason, a very small buffer SiO2 layer is generally desirable between the silicon active area and high-k gate dielectric. Most double gate structures have a silicon sidewall that has crystallographic planes different than the (100) plane. Because the oxidation rate is higher in crystal planes other than (100) due to higher silicon density in those planes and the higher trap state densities in those planes, gate oxide thickness along the silicon sidewalls are generally thicker than along the planar regions. Disadvantageously, this results in poor gate control along the sidewall. Another undesirable effect of growing gate oxide in the sidewall for nanometer scale devices is the decrease in the width of the device due to excessive gate oxide growth. As will be appreciated, decreasing the width of the device generally results in decreased total available drive current.
Embodiments of the present invention may address one or more of the problems set forth above.